1. Field of the Invention
The present invention relates to a circuit, a method, an apparatus and a pattern generation program product used in a burn-in test for an integrated circuit etc.
2. Description of Related Art
With processes of an integrated circuit including VLSI (Very Large Scale Integrated circuit) becoming more and more detailed, circuits are becoming to be more complicated and increasing their sizes. Along with the development, an issue of how to remove a malfunction in the integrated circuit is increasing its importance. Furthermore, a low-cost burn-in test has been demanded by improving test efficiency to perform a burn-in test for many integrated circuits.
Many of integrated circuits including VLSI employs scan design to detect a malfunction. The scan design is to detect a malfunction in an internal combinational circuit that resides between registers by inputting test data from outside the circuit and scanning an operation result using a shift register formed by registers in the circuit connected together. A circuit performing such scan shift and scan capture operations is referred to as a scan test circuit. The scan test circuit is used in a burn-in test because it is able to efficiently activate the internal combinational circuit, which is a circuit to be tested, by continuously inputting test data.
However to operate the scan test circuit, not only a test pattern but many external signals including a clock signal and a signal for controlling scan operation need to be input. Consequently a signal generation feature such as a pulse generator is required in a burn-in test circuit, and wiring of a burn-in test board becomes complicated, thereby generating a high workload of the burn-in test circuit. Therefore, a high performance burn-in test apparatus is needed, and a cost for a burn-in test is increased. Further, with a large number of input signal terminals from outside, the number of integrated circuits to perform the burn-in test at one time is limited and this deteriorates test efficiency as well as increases the cost for the burn-in test.
Examples of techniques for resolying such problem are disclosed in Japanese Unexamined Patent Application Publication Nos. 07-098358, 2004-108881, and 2005-140770. FIG. 8 illustrates a configuration of a burn-in test circuit of Japanese Unexamined Patent Application Publication No. 07-098358. An integrated circuit 50 is configured by four scan flip-flips (hereinafter referred to as a scan FF) 500 501, 502, and 503, internal combinational circuits 504 to 506 connected between the scan FFs 500 to 503, a logical inverted feedback loop circuit 507, and a feedback loop switching circuit 508.
The four scan FFs 500 to 503 form a scan chain by being connected each other in series. The scan FF 503, a front stage of the scan chain, is connected to a normal input terminal (SI1 terminal) of the integrated circuit 50 via the feedback loop switching circuit 508, and the scan FF 500, a last stage, is connected to a normal output terminal (SO1 terminal) of the integrated circuit 50. The internal combinational circuits 504, 505, and 506 are respectively connected between the scan FFS 500 and 501, between 501 and 502, and between 502 and 503, and are activated by output signals from the scan FFs 501, 502, and 503. The output signal from the scan FF 500 is inverted via the logical inverted feedback loop 507, and input to the feedback loop switching circuit 508. On the other hand, a signal from the logical inverted feedback loop circuit 507 or the SI1 terminal is selectively input to the scan chain by the feedback loop switching circuit 508 that operates according to a signal of a test control terminal (TEST terminal).
With the configuration described in the foregoing, the output signal from the scan FF 500 is inverted by the logical inverted feedback loop circuit 507 in a burn-in test, and repetitions of“0” and“1” are input to the scan chain. Accordingly the outputs from the scan FFs 500, 501, 502, and 503 repeat“0” and“1”, thereby efficiently activating the internal combinational circuits 504, 505, and 506.
The burn-in test circuit disclosed in Japanese Unexamined Patent Application Publication No. 07-098358 generates an activation signal in the burn-in test by the logical inverted feedback loop circuit mounted inside the integrated circuit. This therefore reduces the number of input signals from outside the integrated circuit and increases the number of integrated circuits to perform a burn-in test for at one time. Thus an efficiency of the burn-in test can be improved and also cost for the burn-in test can be reduced.
Furthermore, in a burn-in test circuit disclosed in Japanese Unexamined Patent Application Publication No. 2004-108881, the scan shift operation and the scan capture operation are repeated for 2(n−1) cycle in a burn-in test according to a signal generated from a BIST (Built In Self Test) circuit mounted inside the integrated circuit. Accordingly the scan control signal is not necessary to be input from outside the integrated circuit, thereby enabling to perform a burn-in test with small number of terminals. This circuit further enables to activate the circuit without decreasing a toggle rate of the circuit, enabling to apply stress of the burn-in test efficiently.
Furthermore, in a burn-in test circuit disclosed in Japanese Unexamined Patent Application Publication No. 2005-140770, the scan shift operation and the scan shift capture operation is switched by a scan control signal selection output circuit that outputs a scan control signal in a burn-in test. Accordingly the scan control signal is not necessary to be input from outside the integrated circuit, thereby enabling to perform a burn-in test with small number of terminals.
However it has now been discovered that in the burn-in test circuit disclosed in Japanese Unexamined Patent Application Publication No. 07-098358, as the activation signal by the logical inverted feedback loop circuit 507 is a repetition of “0” and “1”, a degree of activation is lower than a random activation operation. Further, as the logical inverted feedback loop circuit is formed inside the integrated circuit, the burn-in test circuit cannot be modified later.
Moreover in Japanese Unexamined Patent Application Publication No. 2004-108881 and Japanese Unexamined Patent Application Publication No. 2005-140770, as complicated circuits including the BIST circuit and the scan control signal selection output circuit are mounted inside the integrated circuit to increase the number of gates in the integrated circuit, a workload of the integrated circuit increases.